The present invention relates to a data verifying method of a flash memory device, and more particularly, to an erase verifying method of a NAND flash memory, which can verify if an erase operation has been normally performed.
Recently, demand for flash memory devices is increasing because they are electrically programmable and erasable and do not require a refresh operation. Further, studies have been actively conducted on high-integration technologies for developing high-capacity memory devices that are capable of storing more data. For the purpose of high integration in a NAND flash memory device, a plurality of memory cells are serially connected to form one string. Unlike a NOR flash memory device, the NAND flash memory device reads data in sequence. The NAND flash memory device performs a program/erase operation using Fowler-Nordheim tunneling. Specifically, the NAND flash memory device performs the program/erase operation by controlling threshold voltages (Vt) of memory cells while injecting electrons into floating gates or discharging electrons from floating gates.
In the NAND flash memory device, it is very important to ensure reliability of memory cells. Particularly, data retention characteristic of the memory cells is considered very important. However, since the NAND flash memory device performs the program/erase operation using F-N tunneling, electrons are trapped in a tunnel oxide layer of the memory cell during repetitive F-N tunneling process. Due to the trapped electrons, the threshold voltage of the memory cell is shifted. Therefore, data stored in the memory cell may be incorrectly read in a read operation, degrading the reliability of the memory device.
The shift of the threshold voltage of the memory cell may be caused by the repetitive F-N tunneling process from the repeated cycling of the program operation and the erase operation. One method for preventing the shift of the threshold voltage of the memory cell is to sufficiently decrease an erase voltage to less than a verify voltage by controlling a bias condition in the program operation and the erase operation. However, the threshold voltage may be shifted because the threshold voltage is also increased as much as a bias voltage.
When a program operation or erase operation of a memory cell of a cell string is completed, charges may or may not exist in the floating gate of the memory cell transistor.
As illustrated in FIG. 1, an erased memory cell exhibits a negative threshold voltage distribution 110, while a programmed memory cell exhibits a positive threshold voltage distribution 120. However, it is almost impossible to monitor the negative threshold voltage of the memory cell. An allowable lowest word line bias voltage in the NAND flash memory device is 0 V because a negative voltage is not used as a word line bias voltage. Therefore, if a threshold voltage of a memory cell is lower than 0V in an erase verify operation performed after the erase operation, the corresponding memory cell is determined as an erased memory cell.
In this way, memory cells having threshold voltages lower than 0V are determined as erased memory cells in the erase verify operation. For example, a memory cell having a threshold voltage of −2V is determined as an erased memory cell, and a memory cell having a threshold voltage of −0.1V is also determined as an erased memory cell. There is no problem with the memory cell having the threshold voltage of −2 V. However, problems may occur in the memory cell having a threshold voltage of −0.1V. The threshold voltage of the erased memory cell may be shifted by the influence of the program or erase operation on adjacent memory cells, or the degradation of the memory cell due to the repetitive program/erase operations on the corresponding memory cell. Therefore, the threshold voltage of the erased memory cell having the threshold voltage close to 0 V is easily shifted above 0 V. Hence, even though a memory cell is determined as an erased memory cells in the erase verify operation, its threshold voltage may increase higher than 0 V due to various factors, thus degrading the reliability of the semiconductor memory device.
FIG. 2 illustrates threshold voltage distributions of memory cells when erase verification is passed.
Due to various factors, the threshold voltage of the memory cell increases when the erase verification is passed. This shifts the threshold voltage of the erased memory cell. As illustrated in FIG. 2, the threshold voltage is shifted from the left 210 to the right 220 and thus an erase verification line is also shifted to the right. In this case, a margin between the erase verify voltage and a read voltage (Vread) used to detect a state of the memory cell is reduced. Therefore, the read operation may be incorrectly performed, caused by a disturb characteristic of the memory cell and a temperature influence. Further, the threshold voltage of the memory cell greatly varies due to the repeated cycling of the program/erase operation or read disturbance. Consequently, it is necessary to ensure an additional margin between the read voltage and the erase verify voltage.